I. Field of the Invention
The present invention relates to computer systems, and more particularly, to a computer architecture for providing efficient management of memory shared by processors in a multiprocessor (MP) system.
II. Related Art
In an MP system with processors which share memory space, the MP system must maintain "coherency" among all data in memory. Data could exist in several different locations, including in a main memory and perhaps in other remote memory locations, such as caches.
Coherency refers to the concept in which each central processing unit (CPU) must have access to the latest data corresponding to a particular address in the shared memory. In other words, if a data line at a certain address is simultaneously shared by one or more caches and/or the main memory, then as the data line is updated or changed in one of the memory locations, the latest data line must be identified and available to all of the CPUs. In this document, data line refers to any information stored in memory, including instructions, processed data or unprocessed data. In order to maintain coherency in a conventional MP system, a bus controller/interface monitors a system bus for reads and writes to memory. When the bus controller detects either a memory read or a memory write, the bus controller initiates a snoop cycle which is directed to all of the caches in the MP system.
The protocol implemented for the snoop cycle depends, in large part, on the types of caches used in the MP system. Conventionally, caches have been classified as either "write-back" (WB) or "write-through" (WT). Recently, some caches have been designed so that they can operate as either a WB or a WT cache depending upon the logical state of an input to the cache.
In a WB cache, data lines are written from the WB cache only when the data lines are requested by some other source. Consequently, a local CPU can change data lines in a local WB cache many times without other memory locations in the MP system knowing of the changes.
If during the snoop cycle it is determined that a certain WB cache has modified data, then the certain WB cache provides the modified data to the requesting CPU. If during the snoop cycle a memory write occurs from the WB cache, one conventional protocol for maintaining coherency is to invalidate the data line at all memory locations other than the receiving memory location. A data line is invalidated by changing the state of a local status bit in the directory of the WB cache. The status bit is oftened referred to as a "valid" bit in the industry.
In WT caches, data lines are "written through" to the main memory upon each update or change of the data lines by any processor. Accordingly, the most current data lines are always in the main memory. As a result, a conventional protocol for maintaining coherency among WT caches is to have the bus controller initiate a snoop cycle only on memory writes. No action need be taken on memory reads from the WT cache. Consequently, when an MP system utilizes WT caches, coherency may be maintained with a lessor number of snoop cycles than with WB caches.
However, the foregoing conventional protocols for maintaining coherency in an MP system using WT or WB caches are problematic. Each time that a snoop cycle is initiated, any CPU accessing a cache must temporarily wait while an inquiry is made of a data line in the cache. Consequently, the performance of CPUs is compromised because of the snoop inquiries.
As more processors are added to the MP system, a higher number of snoop cycles must take place and, consequently, more interactions must occur with the caches. Moreover, the buses of the MP system, including the system bus, are characterized by heavy traffic. Accordingly, in a broad sense, the numerous snoop cycles reduce the number of processors that may be operating in the MP system.